The present invention relates to a method of forming a resist pattern on a substrate, and more particularly, to a method of forming a resist pattern on a metal layer provided on a glass substrate to produce a mask for manufacturing a semiconductor device.
The resist pattern is widely used in the field of semiconductor device. For example, the mask for manufacturing the semiconductor device is produced by following process steps: depositing a metal layer such as a chromium layer on a major surface of the glass substrate, coating a resist film on the metal layer, selectively exposing the resist film by an electron beam, etc., developing the resist film to form the resist pattern, and selectively etching the metal layer by using the resist pattern as an etching mask. On the other hand, in the manufacturing process steps for the semiconductor device, the resist pattern is formed on a conductive layer such as a polycrystalline silicon layer or an aluminum layer or on a insulating layer provided on a semiconductor substrate, that is, a semiconductor wafer, and selectively etching the conductive layer or the insulating layer by using the resist pattern as an etching mask to form electrode wirings or contact holes. In any cases, a precise resist pattern is necessary over the entire area.
However, even if the resist pattern has a precise and designed dimension at one portion, at other portions on the same substrate, the dimensions of the resist pattern are inevitably deviated to some extent from the designed value. The deviation is caused by the previous process steps of coating the resist film, selectively exposing the resist film and developing the resist film. If many specimens (mask substrates or semiconductor wafers) are treated in substantially identical apparatus and with substantially identical conditions in each process step, the specimens have the same distribution of the deviation in the resist pattern over the entire areas, each other. For example, if the resist pattern of one specimen becomes 0.2 .mu.m broader than the designed value at one portion, the other specimens have the same tendency that the respectively resist patterns become about 0.2 .mu.m broader at the corresponding portions. In the prior art, more precise resist pattern over the entire areas cannot be obtained. To realize a high integrated semiconductor device having a fine pattern, the deviation of the dimension in the resist pattern must be compensated over the effective areas of the substrate entirely.